For electrical engineering students studying digital logic who are dissatisfied with the manual method of designing a Finite State Machine (FSM), our "I can design a counter" app automates this time-consuming activity.
Unlike using a set of disconnected tools such as a diagram editor and a Karnaugh map simplifier, we have seamlessly integrated (1) a wizard, (2) a bubble diagram editor, (3) a truth table editor, (4) a Boolean expression minimizer, and (5) a circuit renderer into a single app. This means when you edit the bubble diagram, the table, the expression, and the circuit are instantly updated to match the bubble diagram. This feature permits you to conduct quick experiments in search for the least costly implementation.
The app also contains advanced features such as the ability to specify don't-care transitions and the ability to generate expressions for a J-K flip-flop implementation.
Our app is ideal for you if you are currently taking a course in computer design, since synchronous sequential logic circuit design is a key concept that you will surely encounter at some point during the class.
Version 3.x does everything version 1.x and version 2.x do.
Version 1.x is a free trial-ware
Version 2.0 finds best values to assign to don't-cares.
Version 2.1 can create FSM's that have 2, 4, or 8 states.
Version 2.2 removed leading zeros from bubble labels.
Version 2.3 row 2 of size 4 table shows dashes correctly.
Version 3.0 Added J-K Flip-Flop capability.
Version 3.1 Added circuit drawing capability.